semiconductor msc23cv23218d-xxbs4 2,097,152-word x 32-bit dynamic ram module : fast page mode type this version: mar. 1999 description the msc23cv23218d-xxbs4 is a fully decoded, 2,097,152-word x 32-bit cmos dynamic random access memory module composed of four 16mb drams (1mx16) in tsop packages mounted with eight decoupling capacitors on a 72-pin glass epoxy small outline package. this module supports any application where high density and large capacity of storage memory are required. features 2,097,152-word x 32-bit organization 72-pin small outline dual in-line memory module msc23cv23218d-xxbs4 : gold tab single +3.3v supply 0.3v tolerance input : lvttl compatible output : lvttl compatible, 3-state refresh : 1024cycles/16ms /cas before /ras refresh, hidden refresh, /ras only refresh capab ility fast page mode capab ility product family access time (max.) power dissipation family t rac t aa t cac cycle time (min.) operating (max.) standby (max.) MSC23CV23218D-60BS4 60ns 30ns 15ns 110ns 864mw msc23cv23218d-70bs4 70ns 35ns 20ns 130ns 792mw 7.2mw
semiconductor msc23cv23218d module outline 3.03 5.00 2 r2.0 r2.0 1 3.17 min. 3.80max. (unit : mm) msc23 cv23218d -xxbs 4 *1 the common size difference of the board width 19.78 mm of its height is specified as 0.2. the value above 19.78mm is specified as 0.5. 7 1 *1 3.18 0.1 3 25.40.13 2.0 0.1 3 2.62typ. 59.69 0.2 44.45 0.1 1.00 0.1 7 2 1.8 0.1 17.780.13 51.66 0. 1 44.45 0.1 3.25typ. 2- f 1.8 0.23 min. 0.25 max. 1.270.1 1.0 0. 1
semiconductor msc23cv23218d pin configuration front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 37 dq16 2 dq0 38 dq17 3dq139v ss 4 dq2 40 /cas0 5 dq3 41 /cas2 6 dq4 42 /cas3 7 dq5 43 /cas1 8 dq6 44 /ras0 9 dq7 45 /ras1 10 v cc 46 nc 11 pd1 47 /we 12 a0 48 nc 13 a1 49 dq18 14 a2 50 dq19 15 a3 51 dq20 16 a4 52 dq21 17 a5 53 dq22 18 a6 54 dq23 19a1055nc20nc56dq24 21 dq8 57 dq25 22 dq9 58 dq26 23 dq10 59 dq27 24 dq11 60 dq28 25 dq12 61 v cc 26 dq13 62 dq29 27 dq14 63 dq30 28 a7 64 dq31 29 nc 65 nc 30 v cc 66 pd2 31 a8 67 pd3 32 a9 68 pd4 33 /ras3 69 pd5 34 /ras2 70 pd6 35 dq15 71 pd7 36 nc 72 v ss presence detect pins pin no. pin name -60 -70 11 pd1 nc nc 66 pd2 v ss v ss 67 pd3 v ss v ss 68 pd4 nc nc 69 pd5 nc v ss 70 pd6 nc nc
semiconductor msc23cv23218d block diagram /we /cas1 /cas0 a0-a9 /cas3 /cas2 dq0 a0-a9 dq1 dq3 dq2 dq4 dq5 /ras /lcas /ucas dq6 dq1 dq2 dq3 /ras1 v cc v ss c1-c8 dq8 v ss /we /oe v cc dq4 dq5 dq6 dq7 dq7 dq8 dq9 dq11 dq10 dq12 dq13 dq14 dq9 dq10 dq11 dq16 dq12 dq13 dq14 dq15 dq15 a0-a9 dq1 dq3 dq2 dq4 dq5 /ras /lcas /ucas dq6 dq8 v cc /we /oe v ss dq7 dq9 dq11 dq10 dq12 dq13 dq14 dq16 dq15 /ras0 /ras2 /ras3 dq16 a0-a9 dq1 dq3 dq2 dq4 dq5 /ras /lcas /ucas dq6 dq17 dq18 dq19 dq8 v ss /we /oe v cc dq20 dq21 dq22 dq23 dq7 dq24 dq9 dq11 dq10 dq12 dq13 dq14 dq25 dq26 dq27 dq16 dq28 dq29 dq30 dq31 dq15 a0-a9 dq1 dq3 dq2 dq4 dq5 /ras /lcas /ucas dq6 dq8 v cc /we /oe v ss dq7 dq9 dq11 dq10 dq12 dq13 dq14 dq16 dq15
semiconductor msc23cv23218d electrical characteristics absolute maximum ratings parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to +4.6 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 v short circuit output current i os 50 ma power dissipation p d *4w operating temperature t opr 0 to +70 c storage temperature t stg -40 to +125 c * ta = 25c recommended operat ing conditions ( ta = 0c to +70c ) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 000v input high voltage v ih 2.0 - v cc +0.3 v input low voltage v il -0.3 - 0.8 v capacitance ( v cc = 3.3v 0.3v, ta = 25c, f = 1 mhz ) parameter symbol typ. max. unit input capacitance (a0 - a9) c in1 -31pf input capacitance (/we) c in2 -35pf input capacitance (/ras0- /ras3) c in3 -13pf input capacitance (/cas0- /cas3) c in4 -20pf i/o capacitance (dq0 - dq31) c dq -20pf
semiconductor msc23cv23218d dc characteristics (v cc = 3.3v 0.3v, ta = 0c to +70c ) -60 -70 parameter symbol condition min. max. min. max. unit note input leakage current i li 0v v in v cc +0.3v; all other pins not under test = 0v -40 40 -40 40 a output leakage current i lo dq disable 0v v out v cc -20 20 -20 20 a output high voltage v oh i oh = -2.0ma 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 2.0ma 0 0.4 0 0.4 v average power supply current (operating) i cc1 /ras, /cas cycling, t rc = min. - 240 - 220 ma 1, 2 /ras, /cas = v ih -8-8ma1 power supply current (standby) i cc2 /ras, /cas 3 v cc -0.2v -2-2ma1 average power supply current (/ras only refresh) i cc3 /ras cycling, /cas = v ih , t rc = min. - 240 - 220 ma 1, 2 average power supply current (/cas before /ras refresh) i cc6 /ras cycling, /cas before /ras - 240 - 220 ma 1, 2 average power supply current (fast page mode) i cc7 /ras = v il , /cas cycling, t pc = min. - 170 - 160 ma 1, 3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while /ras = v il . 3. the address can be changed once or less while /cas = v ih .
semiconductor msc23cv23218d ac characteristics (1/2) (v cc = 3.3v 0.3v, ta = 0c to +70c ) note: 1, 2, 3 -60 -70 parameter symbol min. max. min. max. unit note random read or write cycle time t rc 110 - 130 - ns fast page mode cycle time t pc 40 - 45 - ns access time from /ras t rac - 60 - 70 ns 4, 5, 6 access time from /cas t cac - 15 - 20 ns 4, 5 access time from column address t aa - 30 - 35 ns 4, 6 access time from /cas precharge t cpa - 35 - 40 ns 4 output low impedance time from /cas t clz 0-0-ns4 /cas to data output buffer turn-off delay time t off 0 15 0 20 ns 7 transition time t t 3 50 3 50 ns 3 refresh period t ref -16-16ms /ras precharge time t rp 40 - 50 - ns /ras pulse width t ras 60 10k 70 10k ns /ras pulse width (fast page mode) t rasp 60 100k 70 100k ns /ras hold time t rsh 15 - 20 - ns /cas precharge time (fast page mode) t cp 10 - 10 - ns /cas pulse width t cas 15 10k 20 10k ns /cas hold time t csh 60 - 70 - ns /cas to /ras precharge time t crp 5-5-ns /ras hold time from /cas precharge t rhcp 35 - 40 - ns /ras to /cas delay time t rcd 20 45 20 50 ns 5 /ras to column address delay time t rad 15 30 15 35 ns 6 row address set-up time t asr 0-0-ns row address hold time t rah 10 - 10 - ns column address set-up time t asc 0-0-ns column address hold time t cah 10 - 15 - ns column address to /ras lead time t ral 30 - 35 - ns read command set-up time t rcs 0-0-ns read command hold time t rch 0-0-ns8 read command hold time referenced to /ras t rrh 0-0-ns8
semiconductor msc23cv23218d ac characteristics (2/2) (v cc = 3.3v 0.3v, ta = 0c to +70c ) note: 1, 2, 3 -60 -70 parameter symbol min. max. min. max. unit note write command set-up time t wcs 0-0-ns write command hold time t wch 10 - 15 - ns write command pulse width t wp 10 - 10 - ns write command to /ras lead time t rwl 15 - 20 - ns write command to /cas lead time t cwl 15 - 20 - ns data-in set-up time t ds 0-0-ns data-in hold time t dh 10 - 15 - ns /cas active delay time from /ras precharge t rpc 5-5-ns /ras to /cas set-up time (/cas before /ras) t csr 10 - 10 - ns /ras to /cas hold time (/cas before /ras) t chr 10 - 10 - ns
semiconductor msc23cv23218d notes: 1. a start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/ras only refresh or /cas before /ras refresh) before proper device operation is achieved. 2. the ac characteristics assumes t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition time (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1ttl loads and 100pf. the output timing reference levels are v oh = 2.0v and v ol = 0.8v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle.
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